? semiconductor components industries, llc, 2003 october, 2003 ? rev. 6 1 publication order number: NTD60N03/d NTD60N03 power mosfet 60 amps, 28 volts n?channel dpak designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. typical applications ? power supplies ? converters ? power motor controls ? bridge circuits maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss 28 vdc gate?to?source voltage ? continuous v gs 20 vdc drain current ? continuous @ t c = 25 c drain current ? single pulse (t p = 10 s) i d i dm 60* 120 adc total power dissipation @ t c = 25 c p d 75 watts operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 28 vdc, v gs = 10 vdc, i l = 17 apk, l = 5.0 mh, r g = 25 ) e as 733 mj thermal resistance ? junction?to?case ? junction?to?ambient (note 1) ? junction?to?ambient (note 2) r jc r ja r ja 1.65 67 120 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using 1 pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using the minimum recommended pad size, (cu area 0.412 in 2 ). *chip current capability limited by package. device package shipping 2 ordering information NTD60N03 dpak 75 units/rail NTD60N03t4 dpak 2500 tape & reel NTD60N03?1 dpak straight lead 75 units/rail http://onsemi.com n?channel d s g 1 gate 3 source 2 drain 4 drain dpak case 369aa style 2 marking diagrams t4228 device code y = year ww = work week 1 2 3 4 1 gate 3 source 2 drain 4 drain dpak case 369d style 2 1 2 3 4 28 v 6.1 m r ds(on) typ 60 a i d max v (br)dss yww t 4228 yww t 4228 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NTD60N03 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 3) (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 28 ? 30.6 25 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 28 vdc) (v gs = 0 vdc, v ds = 28 vdc, t j = 150 c) i dss ? ? ? ? 1.0 10 adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.9 ?3.8 3.0 ? vdc mv/ c static drain?to?source on?resistance (note 3) (v gs = 10 vdc, i d = 30 adc) (v gs = 4.5 vdc, i d = 30 adc) (v gs = 10 vdc, i d = 10 adc) r ds(on) ? ? ? 6.1 9.2 6.4 7.5 ? ? m forward transconductance (v ds = 15 vdc, i d = 10 adc) (note 3) g fs ? 20 ? mhos dynamic characteristics input capacitance (v 24 vd v 0vd c iss ? 2150 ? pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f=10 mhz) c oss ? 680 ? transfer capacitance f = 1 . 0 mh z ) c rss ? 260 ? switching characteristics (note 4) turn?on delay time t d(on) ? 10 ? ns rise time (v dd = 15 vdc, i d = 15 adc, v 10 vdc t r ? 18 ? turn?off delay time v gs = 10 vdc, r g = 3 . 3 ) t d(off) ? 32 ? fall time r g = 3 . 3 ) t f ? 15 ? gate charge (v 24 vd i 15 ad q t ? 30 ? nc gaec age (v ds = 24 vdc, i d = 15 adc, v gs = 4 5 vdc) (note 3) q1 ? 6.5 ? v gs = 4 . 5 vd c ) (n o t e 3) q2 ? 18.4 ? source?drain diode characteristics forward on?voltage (i s = 2.3 adc, v gs = 0 vdc) (note 3) (i s = 30 adc, v gs = 0 vdc) (i s = 2.3 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? ? 0.75 1.2 0.65 1.0 ? ? vdc reverse recovery time (i 23ad v 0vd t rr ? 39 ? ns e e se eco e y e (i s = 2.3 adc, v gs = 0 vdc, di s /dt = 100 a/ s) (note 3) t a ? 21 ? s di s /dt = 100 a/ s ) (n o t e 3) t b ? 18 ? reverse recovery stored charge q rr ? 0.043 ? c 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NTD60N03 http://onsemi.com 3 1.8 1.4 1.2 0.8 0.0 10 1 100 1000 40 20 50 10 30 0 60 0.005 0 30 2 1.5 1 i d , drain current (amps) 0 v gs , gate?to?source voltage (v) figure 1. on?region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.07 0.05 0.02 0.01 4 0 26810 figure 3. on?resistance versus gate?to?source voltage v gs , gate?to?source voltage (v) figure 4. on?resistance versus drain current and gate voltage i d , drain current (a) r ds(on) , drain?to?source resistance ( ) figure 5. on?resistance variation with temperature t j , junction temperature ( c) figure 6. drain?to?source leakage current versus voltage v ds , drain?to?source voltage (v) i dss , leakage (na) 50 ?50 100 75 0 ?25 125 150 23 6 5 0 0.01 0.015 416 12 820 v ds , drain?to?source voltage (v) 10 20 40 2.5 3 v gs = 0 v t j = 125 c t j = 100 c i d = 30 a v ds = 10 v v gs = 4.5 v v gs = 10 v t j = 25 c i d = 10 a t j = 25 c v ds 10 v t j = 25 c t j = ?55 c t j = 125 c r ds(on) , drain?to?source resistance ( ) r ds(on) , drain?to?source resistance (normalized) t j = 25 c 50 25 45 0.5 4 3.5 4.5 5 v gs = 2.8 v 3 v 3.2 v 3.4 v 3.6 v 3.8 v 4 v 4.5 v 5 v 6 v 8 v 10 v 0.04 0.03 0.06 10 15 20 25 30 1.0 1.6 0.2 0.4 0.6
NTD60N03 http://onsemi.com 4 v gs v ds 4 8 6 0 2 15 2000 10 0 c, capacitance (pf) 0 q g , total gate charge (nc) figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage versus total charge v gs , gate?to?source voltage (v) 1 1000 100 1 10 100 figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( ) figure 10. diode forward voltage versus current v sd , source?to?drain voltage (v) i s , source current (amps) t, time (ns) 5000 08 0.1 0.9 0.7 0.5 0.3 3 1 0 4 5 gate?to?source or drain?to?source voltage (v) 1000 1500 4000 25 2 i d = 15 a t j = 25 c q 2 q 1 v gs q t v dd = 24 v i d = 20 a v gs = 10 v t r t d(off) t d(on) t f v gs = 0 v t j = 25 c v gs = 0 v t j = 25 c c rss c iss c oss c rss c iss 16 24 32 500 2500 3000 3500 4500 10 5 5 15 20 10 v ds = 0 v
NTD60N03 http://onsemi.com 5 figure 11. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 dc 1 100 100 10 10 ms 1 ms 100 s v gs = 10 v single pulse t c = 25 c di/dt t rr t a t p i s 0.25 i s time i s t b figure 12. diode reverse recovery waveform r ja (t) = r(t) r ja d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 13. thermal response ? various duty cycles t, time (seconds) rthja(t), effective transient thermal resistance 1000 1 d = 0.5 1e-05 1e-03 1e-02 1e-01 0.2 0.01 0.01 0.02 0.05 0.1 1e+00 1e+01 1e+03 single pulse 1e-04 1e+02 mounted to minimum recommended footprint duty cycle 100 10 0.1
NTD60N03 http://onsemi.com 6 information for using the dpak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc?59, sc?70/sot?323, sod?123, sot?23, sot?143, sot?223, so?8, so?14, so?16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 14 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 14. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
NTD60N03 http://onsemi.com 7 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 ?189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 15. typical solder heating profile
NTD60N03 http://onsemi.com 8 package dimensions dpak case 369aa?01 issue o style 2: pin 1. gate 2. drain 3. source 4. drain d a b r v s f l 2 pl m 0.13 (0.005) t e c u j ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.025 0.035 0.63 0.88 e 0.018 0.024 0.46 0.61 f 0.033 0.045 0.83 1.14 j 0.018 0.023 0.46 0.58 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 dpak case 369d?01 issue o 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NTD60N03/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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